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VIA's next-generation x86-compatible processor will ship as the C7, the Taiwanese chip maker said today.
Better known by its codename, 'Esther', the part will debut in the first half of 2005 in two forms: the desktop-oriented C7 and the mobile C7-M. To date, the core's official classification has been the C5J.
The mobile and desktop versions will offer the same feature set, VIA said, without elaborating, though the former will also sport the fourth generation of VIA's PowerSaver energy conservation technology. Both chips will add RSA encryption (with Montgomery Multiplier support) and Secure Hashing (SHA-1 and SHA-256) acceleration to the hardwired security-oriented functionality the current C3 chips already provide.
VIA has already said that the C7 will be fabbed by IBM using a 90nm silicon-on-insulator, low-k dielectric process and 300mm wafers. The C7 is expected to consume 35W at 1GHz, but be capable of being clocked to 2GHz and beyond.
The C7 will operate using an 800MHz frontside bus. It will include support for Intel's SSE 2 and 3 multimedia-oriented instruction sets. The chip will get a larger L2 cache than the C3's 64KB, though VIA has yet to say how much.
The new chip will also support Windows XP Service Pack 2's No Execution (NX) feature that is intended to prevent code held in data-only memory blocks from being run
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